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CS8129 5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold
The CS8129 is a precision 5.0 V linear regulator capable of sourcing 750 mA. The RESET threshold voltage has been lowered to 4.2 V so that the regulator can be used with 4.0 V microprocessors. The lower RESET threshold also permits operation under low battery conditions (5.5 V plus a diode). The RESET's delay time is externally programmed using a discrete RC network. During powerup, or when the output goes out of regulation, RESET remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 V. Hysteresis is included in the Delay and the RESET comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regulator is protected against voltage transients ranging from -50 V to +40 V. Short circuit current is limited to 1.2 A (typ). The CS8129 is packaged in a 5 lead TO-220 and a 16 lead surface mount package.
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TO-220 FIVE LEAD T SUFFIX CASE 314D 1 5 TO-220 FIVE LEAD TVA SUFFIX CASE 314K
1
1
TO-220 FIVE LEAD THA SUFFIX CASE 314A 5
* * * * * *
*
5.0 V 3.0% Regulated Output Low Dropout Voltage (0.6 V @ 0.5 A) 750 mA Output Current Capability Reduced RESET Threshold for Use with 4.0 V Microprocessors Externally Programmed RESET Delay Fault Protection - Reverse Battery - 60 V, -50 V Peak Transient Voltage - Short Circuit - Thermal Shutdown Pb-Free Packages are Available*
16 1
SO-16WB DW SUFFIX CASE 751G
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 8 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 8
Publication Order Number: CS8129/D
CS8129
PIN CONNECTIONS
TO-220 5-LEAD Pin 1. VIN 2. RESET 3. GND 4. Delay 5. VOUT VIN NC NC GND GND RESET NC Delay 1 SO-16 WB 16 VOUT NC VOUT(SENSE) GND GND GND NC NC
1
VIN Over Voltage Shutdown VOUT Pre-Regulator Regulated Supply for Circuit Bias Bandgap Reference
Error Amplifier Anti-Saturation and Current Limit - + - + VOUT
(SENSE)
Charge Current Generator
Thermal Shutdown
Delay
Latching Discharge Q - S R
GND
Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS
Rating Input Operating Range Power Dissipation Peak Transient Voltage (46 V Load Dump @ 14 V VIN) Output Current Electrostatic Discharge (Human Body Model) Junction Temperature Storage Temperature Range Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value -0.5 to 26 Internally Limited -50, 60 Internally Limited 4.0 -55 to +150 -55 to +150 260 peak 230 peak Unit V - V - kV C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 second maximum. 2. 60 seconds max above 183C.
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+ -
+ VDISCHARGE Delay Comparator RESET
CS8129
ELECTRICAL CHARACTERISTICS (-40C TA 125C, -40 TJ 150C, 6.0 VIN 26 V, 5.0 mA IOUT 500 mA, RRESET = 4.7 kW to VOUT unless otherwise noted.) (Note 3)
Characteristic OUTPUT STAGE (VOUT) Output Voltage Dropout Voltage Supply Current IOUT = 500 mA IOUT = 10 mA IOUT = 100 mA IOUT = 500 mA 6.0 V VIN 26 V, IOUT = 50 mA 50 mA IOUT 500 mA, VIN = 14 V f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA - - VOUT -0.6 V, 10 W Load Guaranteed by Design - 4.85 - - - - - - 54 0.75 32 -15 150 5.0 0.35 2.0 6.0 55 5.0 10 75 1.20 - -30 180 5.15 0.60 7.0 12 100 50 50 - - 40 - 210 V V mA mA mA mV mV dB A V V C Test Conditions Min Typ Max Unit
Line Regulation Load Regulation Ripple Rejection Current Limit Overvoltage Shutdown Reverse Polarity Input Voltage DC Thermal Shutdown RESET AND DELAY FUNCTIONS Delay Charge Current RESET Threshold RESET Hysteresis Delay Threshold Delay Hysteresis RESET Output Voltage Low RESET Output Leakage Delay Capacitor Discharge Voltage Delay Time
VDELAY = 2.0 V VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) VRH = VRT(ON) - VRT(OFF) Charge, VDC(HI) Discharge, VDC(LO)
-
5.0 4.05 4.00 50 3.25 2.85 200 - - - 16
10 4.35 4.20 150 3.50 3.10 400 0.1 0 0.2 32
15 4.50 4.45 250 3.75 3.35 800 0.4 10 0.5 48
mA V V mV V V mV V mA V ms
1.0 V < VOUT < VRT(L), 3.0 kW to VOUT VOUT > VRT(H) Current Discharge Latched "ON", VOUT > VRT CDELAY = 0.1 mF, (Note 4)
3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. Assuming ideal capacitor. CDelay VDelay Threshold Charge Delay Time + + CDelay 3.5 105 (typ) ICharge
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD # SO-16WB 1 16 4, 5, 11, 12, 13 8 6 14 TO-220 5 LEAD 1 5 3 4 2 N/A LEAD SYMBOL VIN VOUT GND Delay RESET VOUT(SENSE) FUNCTION Unregulated supply voltage to IC. Regulated 5.0 V output. Ground Connection. Timing capacitor for RESET function. CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it's regulated value. Remote sensing of output voltage.
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CS8129
TYPICAL PERFORMANCE CHARACTERISTICS
55 50 45 40 30 25 20 15 10 5 0
0 1 2 3 -40C 25C
RLOAD = 25 W
120 100 80 60 40 20 0
4 5 6 7 8 9 10 0
Room Temp RLOAD = 6.67 W
125C
ICQ. (mA)
ICQ (mA)
35
RLOAD = 10 W
RLOAD = 25 W RLOAD = NO LOAD 1 2 3 4 5 6 7 8 9 10
VIN (V)
VIN (V)
Figure 2. Quiescent Current vs. Input Voltage Over Temperature
5.5 5.0 4.5 4.0 VOUT (V) 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0
0 1 2 25C 3 4 5 6 7 8 9 10 -40C 125C
Figure 3. Quiescent Current vs. Input Voltage Over Load Resistance
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
0 RLOAD = 10 W 1 2 3 4 5 6 7 8 9 10 RLOAD = NO LOAD RLOAD = 6.67 W
RLOAD = 25 W
Room Temp
VIN (V)
VIN (V)
Figure 4. Output Voltage vs. Input Voltage Over Temperature
Figure 5. VOUT vs. VIN Over RLOAD
100 80 60 Line Reg. (mV) 40 20 0 -20 -40 -60 -80 -100
0
VIN = 6-26 V
100 80 Load Regulation (mV) 60 40 20 0 -20 -40 -60 -80 -100
TEMP = 125C VIN = 14 V TEMP = 25C TEMP = -40C
TEMP = 25C TEMP = -40C
TEMP = 125C
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
Output Current (mA)
Output Current (mA)
Figure 6. Line Regulation vs. Output Current
Figure 7. Load Regulation vs. Output Current
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CS8129
900 800 Dropout Voltage (mV) 700
25C
100 90 Quiescent Current (mA) 80 70 60 50 40 30 20 10 0
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 800 -40C VIN = 14 V
600 500 400 300 200 100 0
-40C 125C
125C
25C
Output Current (mA)
Output Current (mA)
Figure 8. Dropout Voltage vs. Output Current
90 80 70 Rejection (dB) ESR (ohms) 60 50 40 30 20 10 0
100 101 102 COUT = 10 mF, ESR = 1.0 W COUT = 10 mF, ESR = 1.0 W IOUT = 250 mA COUT = 10 mF, ESR = 1.0 & 0.1 mF, ESR = 0
Figure 9. Quiescent Current vs. Output Current
103 102 101 100
Stable Region CO = 47/68 mF
10-1 10-2 10-3 10-4
CO = 47 mF CO = 68 mF
103
104
105
106
107
108
100
101
102
103
Frequency (Hz)
Output Current (mA)
Figure 10. Ripple Rejection
VOUT VRT(ON) VRT(OFF)
Figure 11. Output Capacitor ESR
VRH
(1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0 V)
RESET
(1)
(3) VRL
(2)
tDELAY DELAY VDH VDC(HI) VDC(LO) (2) VDIS
Figure 12. RESET Circuit Waveform http://onsemi.com
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CS8129
CIRCUIT DESCRIPTION The CS8129 RESET function has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram on page 2).
Low Voltage Inhibit Circuit
condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(HI).
VIN CIN* 100 nF VOUT CS8129 RESET Delay Delay 0.1 mF GND RRST 4.7 kW COUT** 10 mF to 100 mF
This circuit monitors output voltage, and when output voltage is below the specified minimum causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit.
Reset Delay Circuit
*CIN is required if regulator is far from the power source filter. **COUT is required for stability.
Figure 13. Test & Application Circuit
This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the "Low Voltage Inhibit" circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures that a controlled RESET pulse is generated following detection of an error
The Delay time for the RESET function is calculated from the formula:
Delay time + CDelay VDelay Threshold ICharge 3.2 105
Delay time + CDelay(mF)
If CDelay = 0.1 mF, Delay time (ms) = 32 ms 50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time.
APPLICATION NOTES
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 13 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value.
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CS8129
Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.
CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR
IIN VIN
SMART REGULATOR(R)
Control Features IQ
IOUT VOUT
Figure 14. Single Output Regulator With Key Performance Parameters Labeled
HEAT SINKS
The maximum power dissipation for a single output regulator (Figure 14) is:
PD(max) + VIN(max) * VOUT(min) IOUT(max) ) VIN(max)IQ
(1)
A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA.
RqJA + RqJC ) RqCS ) RqSA
where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
RqJA + 150C * TA PD
(2)
(3)
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
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CS8129
MARKING DIAGRAMS
TO-220 5-LEAD 16 CS8129 AWLYYWWG CS 8129 AWLYWWG 1 1 1 A WL YY, Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package CS8129 AWLYWWG CS 8129 AWLYWWG 1 SO-16 WB
ORDERING INFORMATION
Device CS8129YT5 CS8129YT5G Package TO-220* STRAIGHT TO-220* STRAIGHT (Pb-Free) TO-220* HORIZONTAL TO-220* HORIZONTAL (Pb-Free) TO-220* VERTICAL TO-220* VERTICAL (Pb-Free) SO-16WB SO-16WB (Pb-Free) SO-16WB SO-16WB (Pb-Free) 1000 / Tape & Reel 47 Units / Rail 50 Units / Rail Shipping
CS8129YTHA5 CS8129YTHA5G
CS8129YTVA5 CS8129YTVA5G
CS8129YDW16 CS8129YDW16G CS8129YDWR16 CS8129YDWR16G
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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CS8129
PACKAGE DIMENSIONS
TO-220 CASE 314D-04 ISSUE F
-T- B -Q- B1
DETAIL A-A
SEATING PLANE
C E
U K
12345
A L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B B1 C D E G H J K L Q U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.375 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.977 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 9.525 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 24.810 26.543 8.128 9.271 3.556 3.886 2.667 2.972
G D
5 PL
J H
M
0.356 (0.014)
M
TQ
B B1
DETAIL A-A
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CS8129
PACKAGE DIMENSIONS
TO-220 TVA SUFFIX CASE 314K-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5 MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5
-T- C -Q- B
SEATING PLANE
E
W A L
1 2 3 4 5
U
F K
M J
M
DIM A B C D E F G J K L M Q R S U W
D 0.356 (0.014)
M
5 PL
TQ
G R
S
TO-220 THA SUFFIX CASE 314A-03 ISSUE E
-T- B -P-
OPTIONAL CHAMFER
SEATING PLANE
C E
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827
U
A L
F
K
G
5X
5X
J
D 0.014 (0.356)
M
S TP
M
DIM A B C D E F G J K L Q S U
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CS8129
PACKAGE DIMENSIONS
SO-16 WB CASE 751G-03 ISSUE C
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
D
16 M 9
A
q
H
B
1
8
16X
B TA
S
B B
S
0.25
M
A
h X 45_
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical TO-220 FIVE LEAD 2.1 50 SO-16WB 23 105 Unit C/W C/W
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CS8129/D

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